When using a PLL as an on-chip clock generator, the PLL may be required to lock to a system reference clock at power-on and also acquire lock after clock stop. Due to limitations in the feedback path of the PLL (i.e., the clock distribution tree), it might be possible that the PLL will not lock under certain initial conditions of the filter capacitor (i.e., VCO controlling voltage). This initial condition corresponds to the maximum operating frequency of the VCO. For example, in some prior art PLL circuits, the initial value of the filter capacitor may be the supply voltage Vdd or in others, the system ground. Under such circumstances, the PLL is said to have "runaway" to a maximum operating frequency
FIG. 1 is a block diagram illustrating a prior art PLL circuit 100. PLL circuit 100 may use as a local oscillator a voltage or current controlled oscillator where the frequency of the oscillator varies in proportion to a controlling voltage or current. For the purposes of illustrations the local oscillator of FIG. 1 is illustrated as a Voltage Controlled Oscillator (VCO) 105 whose frequency is controlled by control voltage 106 at filter capacitor 107. However, a current controlled oscillator may be substituted for VCO 105 of FIG. 1.
The output of VCO 105 may be divided in divider 115 and may be further buffered and used to drive clock tree 102. Clock tree 102 may represent the distribution of the clock signal throughout a semiconductor circuit. Due to inherent capacitances, resistances and inductances of semiconductor circuits, propagation delays may be introduced into the clock signal as it passes through clock tree 102.
PLL 100 may be controlled by feeding back the output of divider 115. However, in order to compensate for propagation delays, it may be preferable to feed back the clock signal after it has passed through clock tree 102. An output of clock tree 102 may be tapped off (and divided if necessary by divider 1401) and fed to one of the inputs 1402 of Phase Frequency Detector (PFD) 103. PFD 103 may in turn drive charge pump 114 to charge filter capacitor 107.
The other input 1403 to PFD 103 may comprise system reference clock 104 (or a divided version thereof). PLL 100 thus forms a closed loop negative feedback system. PFD 103 produces corrective signals such that the signals at the inputs 1403 & 1402 to PLL 100 are matched in frequency and phase. In other words, PLL 100 produces signals to adjust the controlling voltage 106 of VCO 105 on filter capacitor 107 such that phase and frequency of clock output (node 1402) is matched in phase and frequency with system reference clock (node 1403).
VCO 105 may have a dynamic range over which it may operate. For example, the range of VCO 105 of FIG. 1 may range from 50 MHz to 1.35 GHz. Such frequencies may correspond to upper and lower bounds of the controlling voltage, as specified in Table I.
TABLE I ______________________________________ Controlling Voltage Frequency of VCO ______________________________________ 0 1.35 GHz Vdd-860 mV 750 MHz Vdd-700 mV 500 MHz Vdd-450 mV 100 MHz Vdd-Vtp to Vdd 0 ______________________________________
Where Vdd is supply voltage and Vtp is transistor threshold voltage. The control voltages and frequencies of Table I are used by way of illustration only and are not intended to limit the scope of the present invention in any way. Control voltage 106, for example, may be set in a reverse fashion to that of Table I (e.g., generate a high frequency at high voltage Vdd and a low frequency at low voltage or ground).
The required operating frequency of VCO 105 may be set at a nominal frequency and the useful range of operation may be approximately 500-750 MHz, in which range VCO 105 provides specified performance (i.e., the desired frequency gain, desired power supply rejection, and the like.)
PLL 100 may generally be in a locked state (e.g., at nominal frequency) where the system reference clock is at a lower frequency to accommodate the lower I/O bandwidths. For example, it may be desired to operate the system reference clock 104 at 100 MHz, clock tree 102 be at 300 MHz and VCO 105 at 600 MHz. These frequencies are provided just as an illustration and by no means limit the scope of the invention. Thus divider 1400 may be set to divide by a ratio of 1:1, divider 115 by a ratio of 1:2 and divider 1401 by a ratio of 1:3. Such ratios may enable PLL 100 to lock with inputs 1402 & 1403 to PFD 103 at 100 MHz each. VCO 105 may be bypassed by MUX 116 for dubugging purposes and a slower clock frequency supplied by system reference 104 applied to clock tree 102.
Node 1403 of PFD 103 may be fed system reference clock 104 at 100 MHz and Node 1402 a lower frequency (divided bypass clock 120 at 33.3 MHz) As a result PFD 103 may indicate, from the fed back signal from clock tree 102 that the input clock signal is too slow. PFD 103 may then drive control voltage 106 to ground which may have the effect of driving VCO 105 faster. When lower frequency bypass clock 120 is removed and VCO 105 is reconnected to clock tree 102, PLL 100 will attempt to again achieve a locked state.
However, since control voltage 106 at filter capacitor 107 is at or near ground, the output of VCO 105 may be at its maximum frequency (e.g., 1.35 GHz). If clock tree 102 cannot transmit such a high frequency signal (e.g., due to low bandwidth caused by internal capacitance, resistance and the like), the output of clock tree 102 may be undeterministic, most probably stuck at one rail or another (i.e., Vdd or ground).
PFD 103 may construe such a state as if VCO 105 were running too slow, and will feedback a signal to make VCO 105 run faster, thus further pushing control voltage 106 at filter capacitor 107 further to ground. Thus, PLL 100 may never lock properly but rather stay in a runaway condition.
Prior art systems have attempted to solve the aforementioned problems using a PLL 200 with a hyperactivity detection circuit (HDC) 290 as illustrated in FIG. 2. Such an analog HDC 290 is described, for example, in Rogers, U.S. Pat. No. 5,220,293, issued Jun. 15, 1993 entitled "High reliability phase-locked loop", assigned to the same assignee as the present application and incorporated herein by reference. In this system, the VCO happens to have a positive slope, meaning that higher control voltages correspond to higher frequencies and vice versa.
The HDC 290 comprises of a delay line 222 formed of a plurality of skewed inverters. These inverters are skewed in such a way as to propagate one edge faster than the other. For example, in the prior art circuit, the delay to propagate the rising edge from the input of the delay line to the output (termed D1) is adjusted to be much more than the delay to propagate the falling edge (termed D2).
When control voltage 206 crosses a predetermined threshold, indicating that the VCO is operating at near its maximum frequency, Schmitt trigger 265 changes state, from a 0 to a 1, generating a rising edge which is propagated along delay line 222. After a delay D1, during which time, if there occurs no activity in the clock tree which triggers resetting pulses in one shot 260, the output 252 of delay line 222 goes to a 1.
The output of delay line 222 turns on transistor 266 and after an additional small delay of inverter 250, turns off latching transistor 254. By these actions, transistor 266 turns on, discharging node 206. During the time capacitor 207 is being discharged, if latching transistor 254 is off, it does not allow any resetting pulses (should they occur) to reset delay line 222.
When capacitor 207 is discharged, and the voltage on node 206 goes below another predetermined value, Schmitt trigger 265 changes state to a 0, corresponding to a minimum operating frequency of VCO 205. The 0 at the output of Schmitt trigger 265 may be propagated along delay line 222 with a delay D2 to the gate of transistor 266, switching it off, and turning on latching transistor 254. Now VCO 205 is allowed to lock again from its lowest operating frequency.
However, if control voltage 206 is above the predetermined threshold of Schmitt trigger 265 and clock tree 202 is operating properly, then it is not desirable to reset VCO 205. Thus, one-shot 260 receives input from clock tree 202 through PFD 203. If one-shot 260 detects activity from clock tree 202 in the form of a clock transition (i.e., low to high, high to low) one-shot 260 produces pulses which drive transistor 267 which pulls the output of Schmitt trigger 265 low and clears the signal from delay line 222.
Clearing thus occurs if the rate of activity is greater than 1/(D1-D2) Hz. Here in lies a potential limitation of the prior art circuit of FIG. 2. When using the prior art HDC 290, PLL 200 cannot be made to lock if the frequency of operation clock tree 202 is less than 1/(D1-D2) Hz.
The system of FIG. 2 may operate satisfactorily in most modes of operation. However, recently, the U.S. Government has promulgated guidelines known as the EnergyStar standard for reducing computer power consumption. In the EnergyStar standard, a computer or system may switch to various levels of rest or "sleep" modes to reduce power consumption by dividing (in effect slowing) the overall system clock by a factor of 64 or some other predetermined number.
If HDC 290 is used in an EnergyStar system, activity from clock tree 202 may be slowed by a factor 64, and the delay (D1-D2) may correspondingly have to be made more than 64 cycles. Such large delay differences between propagating the rising and falling edges may be quite impossible to achieve using the prior art circuit of FIG. 2. As a result, if the delay of delay line 222 (D1-D2) is not greater than the factor of 64, HDC 290 may erroneously reset control voltage 206 of filter capacitor 207 when the system is in an energy conservation mode.